The miniaturization or downsizing of VLSI component like MOSFETs is often hindered by physical, technological and economical limitations. The issues are more severe when the minimum features of the active devices are going to shift to dimensions below 0.25 μm, the so called ultra-deep submicron (UDSM) technology. Designing analog circuits on deep sub-micron process technologies (32,22, 14, 10, 7, 5 nm) has its own set of challenges. With supply voltage scaling down, threshold voltages holding its values to maintain moderate leakage currents as demanded by low power designs for modern and mobile gadgets, the headroom is running out.
This downsizing allows minimizing transistor dimensions and increasing the number of devices per chip. To ensure Moore’s law below 100 nm technology nodes both front- and back-end processing has to face technological challenges. This proposed program reviews some of the current research efforts to present less cost-effective solutions.
Course consists of series of lectures on the following topics along with hands on